1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device, such as a semiconductor integrated circuit device, having Spin On Glass film (it is called hereinafter SOG film) that is suitable for multilevel interconnection structure to achieve high integration and a method of fabricating thereof.
This application is a counterpart of Japanese patent application, Ser. No. 192584/1999, filed Nov. 7, 1999, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In a multilevel interconnection technique of a semiconductor device, a multilevel interconnection structure can be obtained by forming an interlevel insulator between a lower wiring and an upper wiring, wherein the lower wiring is formed over a semiconductor substrate and the upper wiring is formed over the lower wiring. An integration of the semiconductor device can be improved by the multilevel interconnection structure.
In general, an electrical junction part is formed in a contact hole which is provided in the interlevel insulator so as to expose an active region of the semiconductor substrate.
There is a self-alignment contact technique to provide such contact hole. This self-alignment technique is executed by following steps.
First, a pair of gate electrodes whose side surfaces and upper surfaces are covered with protection films, e.g., a silicon nitride film, is formed over a semiconductor substrate.
Next, an interlevel insulator is formed over the entire surface of the semiconductor substrate so as to cover the gate electrodes and the protection films.
Next, an etching mask having an opening is formed on a surface of the interlevel insulator so that the opening corresponds to an active region of the semiconductor substrate between the gate electrodes.
Then, an etching process is executed by using the etching mask to form a contact hole extending from the active region to an upper surface of the interlevel insulator. At this time, since the protection films have a high etching-resistance characteristic against an etching gas, or the like, the protection films are prevented from being etching. This means that the protection films function as an etching mask.
In the self-alignment contact technique, even though the etching mask is formed on a position which is slightly different from a desired position, the contact hole exposing the active region can be obtained because of a mask function of the protection film.
However, an anisotropic etching is used for a selective etching process using the etching mask wherein the anisotropic etching is an etching that an etching rate in a direction horizontal is relatively smaller than the etching rate in a direction vertical. Therefore, when a large amount of mask misalignment occurs, there is a possibility that an area of the exposed active region become smaller than an area having a desired value.
The reduction of the exposed active region causes an increase in the contact resistance between the exposed active region and a conductive part which is formed within the contact hole. This means also that electrical characteristics become uneven among contact holes.
In order to overcome such problems mentioned above, an idea that an isotropic etching is used for the selective etching instead of the anisotropic etching may arise. However, when only the isotropic etching is simply applied to the selective etching to form the contact hole in the interlayer insulator, it is difficult to control the area of the exposed active region and the depth of the contact hole. This means that a required contact hole is not obtained.
Another idea that both of the isotropic etching and the anisotropic etching is applied to the selective etching may also arise. However, it is not realistic that the interlayer insulator having single etching-resistance property is subjected to different kinds of etching methods, i.e., the isotropic etching and the anisotropic etching.
Consequently, there has been a need for a semiconductor device having improved electric characteristics and a method of fabricating the same.